Transmission/reception digital circuit in cdma system

ABSTRACT

The present invention relates to a digital transmitting/receiving circuit ( 1 ) intended to be mounted on at least one source and on at least one concentrator exchanging binary symbols with the said sources, the said circuit ( 1 ) comprising a transmitter ( 2 ) capable of transmitting the said binary symbols and a receiver ( 4 ) capable of receiving symbols transmitted by a source, the circuit ( 1 ) being characterized in that the transmitter ( 2 ) comprises a first module ( 20 ) intended to generate at least one binary code for effecting the spectral spreading of symbols to be transmitted and a second module ( 22 ) intended to generate at least one internal clock signal for synchronizing the reception of symbols transmitted by a source, and in that the said receiver comprises means ( 46, 48 ) for detecting new sources of transmission and means ( 49 ) for generating synchronization signals and power control signals corresponding to each new source detected.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention lies in the field of digital transmissionsby direct sequence spectrum spreading in a CDMA (Code Division MultipleAccess) system, that is, a system for multiple access by synchronous orquasi-synchronous code division.

[0002] More particularly, the invention relates to a digitaltransmitting/receiving circuit intended to be mounted on at least onesource and on at least one concentrator exchanging binary symbols withthe said source by a CDMA transmission, the said circuit comprising atransmitter capable of transmitting the said binary symbols and areceiver capable of receiving transmitted symbols.

[0003] The invention finds application in mobile radiocommunicationsystems in wireless local area networks, in wireless local subscriberloops, in cable television, etc.

DESCRIPTION OF THE PRIOR ART

[0004] A synchronous CDMA system is composed of a set of transmitters,usually termed “modems”, and a receiver, usually termed “concentrator”.The transmission of information from the modems to the concentratortakes place along a path termed the uplink, and the transmission ofinformation from the concentrator to the modems via a path termed thedownlink. Several modems can start an acquisition simultaneously. Forthe link to be synchronous, the items of information relating to eachmodem, transmitted on the uplink, have to arrive at the concentrator ina synchronized manner, so that the symbols are superposed and thecorrelation peaks on the different codes are positioned at the samemoment in the symbol window.

[0005] During the transmission phase, one or more codes are allocated toeach modem in order for them to transmit their information at a ratecompatible with its demand. The codes used are perfectly mutuallyorthogonal, in order for the intercorrelation noise to be null when thecodes are synchronized. On reception, the concentrator decodes thereceived signal by using the same codes as those of the modems in orderto extract from them the useful binary information.

[0006] A synchronous reception of the transmitted codes necessitates theuse of a symbol clock set relative to a predetermined reference clock.The synchronization of the different modems then consists of determiningthe shift of each transmitted code with respect to the reference clock,and setting the symbol clock relative to the reference clock.

[0007] Components are at present commercially available for controllinga synchronous CDMA type link.

[0008] There can be mentioned, for example:

[0009] the component HFA 3860 of the Harris company;

[0010] the component SC2001 of the Sirius Communications company.

[0011] The HPA 3860 circuit is essentially oriented toward apoint-to-point link and does not comprise specific resources forcontrolling a link in a synchronous CDMA system.

[0012] Furthermore, in the HFA 3860 component, the symbol clock isprovided in a transmission preamble associated with the flow oftransmitted data. This results in a rate limitation to the extent towhich it occupies a portion of the transmission band.

[0013] In the SC2001 component, the determination of the correlationpeaks on the different codes is effected by an external DSP (DigitalSignal Processing) and microprocessor. The use of this circuit iscomplex, since it does not incorporate all the functions necessary forthe control of a synchronous CDMA communication. More particularly, thiscircuit does not comprise a resource permitting the control of symbolclocks, the demodulation of the received codes, and the calculation ofclock shift instructions, and permits treatment of only two codessimultaneously.

[0014] An object of the invention is to remedy the abovementioneddisadvantages by means of a programmable circuit capable of ensuring allthe necessary functions to effect transmission and reception in asynchronous CDMA system and to automatically manage new accesses.

[0015] These objects are attained by means of a digital circuitcomprising a transmitter for symbols previously spread by a plurality ofbinary codes and a receiver capable of receiving such symbols,characterized in that the transmitter comprises a first module intendedto generate at least one binary code for performing the spectralspreading of the symbols to be transmitted and a second module intendedto generate at least one internal clock signal for synchronizing thereception of the symbols transmitted by a source, and in that the saidreceiver comprises a third module intended to detect new transmissionsources and power control signals corresponding to each new sourcedetected.

[0016] According to the invention the said receiver comprises an inputstage, an acquisition control stage and a traffic control stage, theinput stage comprising a block for editing received data, a pulse filterfor limiting the received signal spectrum, a filtered data samplingstage, and transmitting filtered data on the one hand to the acquisitioncontrol stage, which extracts from the said data, power and time offsetinformation of the received signals with respect to the base clock ofthe receiver, and on the other hand to the traffic control stage, whichextracts from the said data the transmitted binary information and thepower and time offset information of the received signals with respectto the base clock of the receiver.

[0017] According to the invention, the acquisition control stagecomprises a differential demodulation module, a generating module for anacquisition signal representing synchronization signals and powercontrol signals corresponding to each new transmission source, and aprocessing module for the generated acquisition signal.

[0018] According to the invention, the traffic control stage comprises acorrelation module for data previously processed with the codesassociated with these data, a differential demodulation module for thecorrelated data, a calculating module intended to determine thesynchronization signals and the power control signals corresponding toeach new source of transmission detected.

[0019] Other characteristics and advantages of the invention will becomeapparent from the following description, taken as a non-limitingexample, and with reference to the accompanying Figures.

[0020]FIG. 1 shows a block diagram of the circuit according to theinvention;

[0021]FIG. 2 shows a detailed block diagram of a transmitter integratedinto the circuit of FIG. 1;

[0022]FIGS. 3 and 4 shows signals illustrating the operation of thetransmitter according to the invention respectively in acquisition modeand traffic mode;

[0023]FIG. 5 shows a detailed block diagram of a receiver incorporatedinto the circuit of FIG. 1;

[0024]FIG. 6 shows a block diagram of an input stage incorporated intothe circuit of FIG. 5;

[0025]FIG. 7 shows a block diagram of an acquisition control stageincorporated into the circuit of FIG. 5;

[0026]FIG. 8 illustrates the signals processed in the acquisitioncontrol stage of FIG. 7;

[0027]FIG. 9 shows the internal architecture of a selection block and afiltering block incorporated into the acquisition control stage of FIG.7;

[0028]FIG. 10 shows a detailed block diagram of the traffic controlstage of FIG. 5;

[0029]FIGS. 11 and 12 respectively show the internal architecturestructure of a first and a second selection block, mounted in cascaderespectively with a first and second filtering block with which thetraffic control stage of FIG. 10 is equipped;

[0030]FIG. 13 illustrates the coding of the power control according tothe invention.

[0031]FIG. 1 shows a digital transmitting/receiving circuit 1,comprising a transmitter 2 capable of transmitting the binary symbolsspread by the spreading codes and a receiver 4 capable of receivingbinary symbols transmitted by a source.

[0032] The circuit 1 is intended to equip a plurality of sources in aCDMA system, such as for example modems, exchanging binary symbols witha concentrator. The concentrator likewise comprises a circuit 1identical to that of the sources.

[0033] The modem which wishes to start a transmission transmitsinformation modulated with a specific acquisition code which is the samefor all the modems; the items of information arriving at theconcentrator are demodulated in order to extract from them:

[0034] the number of transmitting sources,

[0035] the power of the principal source, that is, the source demandingthe strongest power,

[0036] the shift of the transmitted symbols with respect to thereference symbol clock of the principal source, that is, the clock whichprovides a synchronizing signal for symbols transmitted by the principalcourse. This shift information is transmitted via the downlink to thetransmitting modem in order for this to adjust its symbol reference tothe reference provided by the symbol clock of the principal source.

[0037] The transmitter 2 comprises a data entry block 6, mounted incascade with a data parallelization block 8, a differential modulationblock 10, a spreading block 12, a summation block 14, and a first pulsefilter 16.

[0038] A first module 20 provides to the spreading block 12, binarycodes for performing the spreading of symbols to be transmitted, and asecond module 22 generates an internal clock signal. The first module 20comprises a table 24 comprising a plurality of codes and a codeallocation mask 26 which permits selecting the codes used in thetransmitter 2. The binary rate of the transmitter 2 is directlyconnected to the number of validated codes in the mask 26.

[0039] The receiver 4 comprises an input stage 30, an acquisitioncontrol stage 40, and a traffic control stage 42. The input stage 30comprises a received signal shaping block 32, a pulse filter 34 intendedto limit the spectrum of the received signals, and a filtered signalsampling stage 36. The input stage 30 transmits, on the one hand, thepreviously processed baseband data (rxa_i, rxa_(—q)) to the acquisitioncontrol stage 40 which extracts from them the power and time shiftinformation of the received symbols with respect to the base clock ofthe receiver 4, and on the other hand the data (rxt_i, rxt_q) at thetraffic control stage 42 which extracts from them the transmitted binarydata and the power and time shift information of the received signalswith respect to the base clock (rx_ckref) of the receiver 4.

[0040] The acquisition control stage 40 comprises a first differentialmodulation module 44, an acquisition signal generating module 46, and amodule 48 for processing the generated signal. The module 48 permitsdetecting the access of new sources to the transmission channel andgenerates synchronization signals and power control signalscorresponding to each new source detected. A first clock control blockpermits generating a local symbol clock (rxa_symb_clock) and calculatingthe time shift of the received symbols with respect to a receiverreference clock (rx_ckref).

[0041] The traffic control stage 42 comprises a correlation stage 50comprising a first path M, a second path E, and a third path L. Thepaths M, E, L respectively transmit correlated data corr_m, corr_e andcorr_l to a second differential demodulation stage 52 which transmitsthe demodulated data to a calculation stage 54 intended to determine thesynchronization signals and the power control signals corresponding toeach transmission source. A second clock control block 58 permitspiloting the whole of the traffic control stage 42, either directly bythe reference symbol clock (rx_ckref), in the case of a synchronous CDMAapplication; or by the local symbol clock (rxa_symb_clock) of theacquisition control block (40) in the case of a point-to-pointapplication (asynchronous link).

[0042] A programming module 59, accessible via a simple interfacecomprising an address bus and a data bus, permits programming thedifferent operators of the circuit as a function of the desired use.

[0043] Four modulation formats may be used during transmission: BPSK(Binary Phase Shift Keying), DBPSK (Differential Binary Phase ShiftKeying), QPSK (Quaternary Phase Shift Keying), or DQPSK (DifferentialQuaternary Phase Shift Keying). BPSK and QPSK modulations are accessibleby programming. In QPSK, two useful bits per symbol and per code aretransmitted, necessitating regrouping the entering data by packets oftwo bits “I” and “Q”. In BPSK, a single useful bit is transmitted persymbol and per code. The entering data are copied onto I and Q, then inthe rest of the transmission chain, everything is the same as for QPSKmodulation.

[0044] The base PSK modulation may be transformed into DPSK modulationby a process of differential encoding by simple programming. The binarydata, grouped in two-bit symbols, are differentially coded according tothe IEEE 802.11 and DVB standards.

[0045]FIG. 2 shows a detailed diagram of the transmitter 2.

[0046] The inputs and outputs relating to the transmitter are:

[0047] With the exterior:

[0048] tx_ck: base clock of the transmitter 2;

[0049] tx_resetb: initialization command;

[0050] tx_off: command for interruption of transmission;

[0051] tx_traffic: command for traffic or acquisition mode;

[0052] tx_data: input of binary data;

[0053] tx_ensymb: symbol validation command;

[0054] tx_endata: data validation command;

[0055] tx_ckdac: sample clock for analog-digital converters;

[0056] tx_i: transmitter output path I,

[0057] tx_q: transmitter output path Q.

[0058] With the receiver input stage:

[0059] tx_iint: internal looping of the transmitter output path I;

[0060] tx_qint: internal looping of the transmitter output path Q;

[0061] The transmitter 2 is made operational by the programming of thespreading codes (TX codes), of the code selection mask (TX code mask),and of the symbol clock setting instruction (TX clock shift).

[0062] The transmitter 2, thus programmed, is ready to process threesources of binary data corresponding to three different operating modes:

[0063] a mode termed EXTERNAL in which a serial bit stream from theexterior enters via the tx_data port. The data are presented to thecircuit through a buffer having a rate compatible with the binary rateof the transmitter 2. The latter acts on the buffer by means of thevalidation signal tx_endata and of a data sampling clock signaltx_ckdata. The tx_ensymb signal marks with the code 0 the data whichwill be spread,

[0064] a mode termed INTERNAL, in which a 2⁹⁻¹ pseudo-random pattern isinternally generated from a shift register, for various purposes, forexample self-test of the component,

[0065] a mode termed ACQUISITION, in which a pattern composed of zerosleads to modulating symbols always equal to (0, 0) and thus to thetransmission of unmodulated codes. In this case, the differential coderis forced to “0”.

[0066] In operation, the transmitter 2 receives a clock signal tx_ck,which can have a frequency which is a multiple of the sample frequency.

[0067] The signal tx_resetb activates the operation of the whole of thetransmitter 2. When tx_resetb=0, no clock signal is distributed, and thetransmitter is not operational. When tx_resetb goes to “1”, thetransmitter 2 becomes operational and is initialized.

[0068] The sampling clock signal tx_cksample is generated inside thecircuit by the module 22. This signal is transmitted to the exterior ofthe circuit via the terminal tx_ckdac, for possible piloting ofdigital-analog converters situated upstream of the RF portion of thetransmitter 2.

[0069] The module 22 likewise generates a symbol clock symbol_clock fromprogramming words defining the symbol length.

[0070] This symbol clock may be adjusted by means of specificprogramming.

[0071] This setting command has as its purpose to synchronize the codesin the region of the receiver 4. The accuracy of resetting the clock is{fraction (1/16)}th of a pulse.

[0072] The circuit should remain operational during the phase ofchanging the instruction: tx_resetb=1.

[0073] Whatever the mode of operation, TRAFFIC or ACQUISITION, settingdoes not cause the loss of a symbol, whether the symbol is lengthened(negative instruction) or shortened (positive instruction).

[0074] A 32-bit register contains the mask: mask_tx (31; 0). If the bitmask mask_tx(i)=1, then the code i is valid; if not, the code i is notused.

[0075] The mask is used:

[0076] for generating the validation signal tx_endata, which will causethe binary data buffer to transmit,

[0077] to validate the corresponding spreading output paths.

[0078] When the mask is modified, the new instruction is taken intoaccount immediately at the level of spreading. On the contrary, the nexttx_ensymb is awaited to modify the validation signal tx_endata.

[0079] The thirty-two codes available in the transmitter 2 are stored ina RAM memory. Spreading is effected for each code, the same code beingused for the paths I and Q. Spreading, for a given code, consists ofmultiplying the items of information I and Q at the differential codingoutput by different code coefficients so as to pass from a symbolfrequency signal to a pulse frequency signal (or “chip”).

[0080] The spread signal, for a given code, takes the value +1 or −1during a single sample for each pulse and the null value for the othersamples. As a function of the mask, the spread items of information arethen summed, then passed to the pulse filter 16.

[0081] So as to limit the spectrum of the transmitted signal and tolimit interference between pulses, a low-pass transmission filter isused which gives a particular shape to the pulse.

[0082] This pulse can be:

[0083] a rectangular pulse; in this case, the filter has an spc (sampleper chip) length of the number of samples per pulse, all thecoefficients being equal to 1.

[0084] a pulse corresponding to a square-root raised cosine transferfunction (SRRC) with a damping coefficient equal to 0.4.

[0085] As has been stated previously, the transmitter 2 enables the twoessential phases of a synchronous CDMA transmission to be controlled,the acquisition phase and the traffic phase. The selection of one ofthese two phases is made by means of the external command tx_traffic.

[0086] In the ACQUISITION mode (tx_traffic=0):

[0087] a single code is allocated to the transmitter 2, by means of themask (a priori, the code 0),

[0088] null symbols are generated internally at the level of control ofentering data; the ACQUISITION mode is used. The transmitter 2implements spreading and pulse filtering.

[0089] In the TRAFFIC mode (rtx_traffic=1):

[0090] a certain number of codes are allocated to the transmitter 2 bymeans of the mask,

[0091] the transmitter 2 controls taking into account of the binary data(the entering data are acquired according to the EXTERNAL mode),performs modulation and spreading on the different codes, sums thespread items of information and applies the pulse filter.

[0092] The transmission can be interrupted by an external command,tx_off.

[0093] When tx_off=1, the transmitter 2 stops the transmission, and whentx_off=0, the transmitter 2 resumes transmission.

[0094] In the traffic phase, the rate of a source can be adapted bymodifying the number of codes assigned to it.

[0095] Two procedures can be envisaged for modifying the mask:

[0096] with interruption of the transmission: the new mask being loadedduring this interruption,

[0097] without interruption of the transmission: the new mask is loadedduring transmission.

[0098]FIG. 5 shows a diagram of the receiver 4 comprising the inputstage 30, the acquisition control stage 40, and the traffic controlstage 42.

[0099] As has been said previously, the input stage 30 performs theshaping of the baseband signals and transmits them to the acquisitionstage 40 and to the traffic stage 42.

[0100] The basic functions of the input stage 30 are:

[0101] control of the clocks;

[0102] generation of clocks for the acquisition control stage 40 and thetraffic control stage 42;

[0103] shaping the baseband signals;

[0104] pulse filtering;

[0105] sampling the filtered signals and transferring processed signalsand clock signals to the acquisition control 40 stage and trafficcontrol stage 42.

[0106]FIG. 6 illustrates the internal architecture of the input stage30.

[0107] The inputs and outputs relating to this stage are:

[0108] with the exterior

[0109] rx_ck: base clock of the receiver 4,

[0110] rx_resetb: reset to zero for initialization,

[0111] rx_i: input of receiver 4 path I,

[0112] rx_q: input of receiver 4 path Q,

[0113] rx_ckadc: sample clock for analog-digital converters,

[0114] rx_satent: saturation in shaping of input data.

[0115] With the transmitter 2:

[0116] tx_iint: internal looping of the output of the transmitter 2,path I,

[0117] tx_qint: internal looping of the output of the transmitter 2,path Q.

[0118] With the acquisition stage 40,

[0119] rxa_ckint: base clock of the acquisition stage 40,

[0120] rxa_i: baseband information of path I.

[0121] rxa_q: baseband information of path Q.

[0122] With the traffic control stage 42,

[0123] rxt_ckint: base clock of the traffic control stage 42,

[0124] rxt_i: baseband information of path I.

[0125] rxt_tq: baseband information of path Q.

[0126] In operation, the receiver 4 receives the clock rx_ck, which is aclock at the sampling frequency. The signal rx_resetb activates theoperation of the whole of the receiver 4. When rx_resetb=0, no clocksignal is distributed, and the receiver 4 is not operational. Whenrx_resetb goes to “1”, the receiver 4 becomes operational and isinitialized.

[0127] The sample clock rx_ck is transmitted outside the circuit 1 viathe terminal rx_ckadc for possible piloting of analog/digital converterssituated downstream of the RF portion of the receiver 4.

[0128] The I and Q baseband information is presented in parallel to thereceiver 4 on ports rx_i and rx_q.

[0129] A shift is added to the input data.

[0130] A second pulse filter 34, identical to that of the transmitter 2,is incorporated into the receiver 4. The “chip” pulse may be:

[0131] a rectangular pulse; in this case, the filter length is spc(number of samples per pulse) and all the coefficients are equal to 1.

[0132] a pulse corresponding to a square-root raised cosine (SRRC)transfer function with a damping coefficient equal to 0.4.

[0133] The sample clock rx_ck of the input stage 30 is passed to thetraffic control stage 42 of the receiver 4 (rxt_ckint), and to theacquisition stage 40 of the receiver 4 (rxa_ckint).

[0134] At the output of the input stage 30, two distinct streams of data(rxa_i, rxa_q) and (rxt_i, rxt_q) are respectively transmitted to theacquisition control stage 40 and to the traffic control stage 42 as wellas two clocks rxa_ckint and rxt_ckint.

[0135]FIG. 7 illustrates in detail the internal architecture of theacquisition stage 40 of the receiver 4. This stage receives the basebandinformation preprocessed at the input stage 30 and makes use of it toextract power and clock shift information, respectively, from it bymeans of the calculation module 48 and of the first clock control module49.

[0136] The basic functions of the acquisition stage 40 are:

[0137] differential demodulation

[0138] correlation of baseband information with the acquisitionsequence,

[0139] differential multiplication,

[0140] generation of the acquisition signal (or channel estimation),

[0141] signal selection,

[0142] low-pass filter,

[0143] thresholding,

[0144] processing the acquisition signal,

[0145] detection of correlation peaks (number of sources),

[0146] power estimation,

[0147] control of symbol clocks,

[0148] evaluation of the clock shift command,

[0149] determination of received binary data,

[0150] output of clocks and data,

[0151] display of internal signals.

[0152] The inputs and outputs relating to the acquisition stage 40 are:

[0153] With the exterior:

[0154] rx_resetb: reset to zero for initialization

[0155] rx_ckref: reference symbol clock,

[0156] rxa_ck: acquisition path clock,

[0157] rxa_ensymb: symbol enable,

[0158] rxa_data: binary data,

[0159] rxa_power: power

[0160] rxa_nbacc: number of peaks detected,

[0161] rxa-shift: symbol clock shift information,

[0162] rxa_sync: indication of synchronization with respect to localsymbol clock,

[0163] rxa_caf: automatic frequency control information,

[0164] rxa_errber: data generator error indication,

[0165] rxa_ts: output port for signal observability.

[0166] With the input stage 30 of the receiver 4:

[0167] rxa_ckint: base clock of acquisition stage 40,

[0168] rxa_i: acquisition stage input path I,

[0169] rxa_q: acquisition stage input path Q.

[0170] With the traffic stage of the receiver 4,

[0171] rxa_symb_clock: local symbol clock for asynchronous linking.

[0172] When the acquisition stage 40 is made operational by theprogramming of an acquisition sequence (Rx acquisition code), a matchedfilter 70 integrated into the differential demodulation module 44performs the correlation between the baseband information after shaping,rxa_i and rxa_q, and the acquisition sequence. The maximum length of thecorrelation sequence is 128 pulses. The matched filter is formed by 256shift registers, enabling all the samples of a symbol to be permanentlystored. These registers are grouped in twos. A coefficient of thesequence is applied at the outputs of these pairs of registers toproduce a multiplication by 0, +1 or −1.

[0173] A differential multiplication block 72 integrated into thedemodulation module 44 calculates the dot and cross signals from theoutputs of matched filters, dot being the real portion of the result ofthe complex multiplication of the output of the matched filter and thissame output delayed by the duration of a symbol, cross being theimaginary portion.

[0174] The following equations illustrate the calculation performed,with I(n) and Q(n) corresponding to the outputs of the matched filterand I(n−1) and Q(n−1) to the delayed outputs:

dot=I(n)I(n−1)+Q(n)Q(n−1)

cross=I(n−1)Q(n)−I(n)Q(n−1)

[0175]FIG. 8 illustrates the signals processed in the acquisition stage40, particularly the correlation outputs mf_i and mf_q and the resultsof the differential demodulation: dot and cross.

[0176]FIG. 9 illustrates the internal architecture of the selectionblock 74 and of the filtering block 76. The acquisition signalcorresponds to the estimate of the pulse response of the transmissionchannel (see Patent Application No. 96.15569 filed by the Applicant:“Method of information transmission by pulse response and correspondingreceiver”. Programming permits choosing as useful signal for acquisitionone of the following signals:

[0177] dot: unmodulated code, corresponding for the transmitter 2 to theACQUISITION mode of operation with internal generation of null symbols;the correlation peaks are on the dot signal and are positive,

[0178] abs(dot): code modulated in DBPSK, permitting transmission ofdata on the acquisition code with a better signal-to-noise ratio than inthe DQPSK case,

[0179] MAX (abs(dot), abs(cross)): code modulated in DQPSK, conventionalcase used when the code is modulated.

[0180] Whatever signal is chosen, its value at the level of a peak isrepresentative of the received power for the corresponding access, butis noisy.

[0181] The previously selected signal is strongly affected by multipleaccess noise when the load is high. The low-pass filter 76 permitsperforming a filtering of this signal so as to increase the detectionprobability of access peaks and to improve the estimation of thereceived power for this access.

[0182] A recursive low-pass filter of programmable depth (up to 512symbols, value defined by programming) is used to reduce the noise. Theoutput of the filter 76 gives an estimate of the non-thresholded pulseresponse of the transmission channel; this signal is named rimp.

[0183] The rimp signal coming from the low-pass filter 76 is thenthresholded in the block 78 by means of a program word. The thresholdedsignal rimp_thres is then defined by:

[0184] if rimp≧acquisition threshold, then rimp_thres=rimp,

[0185] if not, rimp_thres=0.

[0186] The signal rimp_thres is analyzed in each symbol window in orderto determine:

[0187] the number of peaks present,

[0188] the position and amplitude of the principal peak.

[0189] Beforehand, the signal rimp_thres is processed so as to preserveonly the maximum values of the peaks represented by a new signalrimp_pond; by means of this new signal rimp_pond, the number of peaksexceeding the acquisition threshold may easily be counted, and definesthe number of transmitters in acquisition phase or the access number.This information coded on two bits is transmitted by the circuit 1, inserial form, via the port rxa_nbacc to each symbol (LSB then MSB).

[0190] The following table illustrates the coding of the access number.coded information number of accesses detected 00 0 01 1 10 2 11 morethan 2

[0191] A search mechanism for the maximum of the signal rimp_threspermits defining the position of the principal peak in the symbolwindow: mean_peak_position. This information is then transmitted to thefirst clock control module 49 to permit resetting it.

[0192] The amplitude of the principal peak (rimp max), in the symbolwindow, is internally stored and is emitted from the circuit 1 for eachsymbol in serial form via the port rxa_power.

[0193] A counter incorporated in the first clock control module 49 isincremented for each sample and constitutes the basis for generating thelocal symbol clock 82 (FIG. 7). Denoting by N the number of pulses persymbol and by spc the number of samples per pulse, in a stable phase,that is, when the principal peak always appears at the same position inthe symbol window, counting is performed from “0”to “N*spc−1”, and thelocal clock edge is generated when the counter passes the value“(N*spc−1)/2”.

[0194] During the dynamic phase corresponding to the appearance,disappearance and slipping of the principal peak, the counter can beloaded with an initial value different from “0”, permitting resettingthe local symbol clock.

[0195] The mechanism of searching for the maximum on the rimp_thressignal during a symbol window permits defining the position of theprincipal peak in the symbol window, mean_peak_position, delivered atthe output of a peak detection block 80 (FIG. 7) incorporated in theacquisition module 48. The position corresponds to the clock shift valuein number of samples. From this information, calculated for each symbol,two methods may be used for resetting the local symbol clock counter 82(FIG. 9), that is, for defining the initial value:

[0196] rapid locking: the initial value is equal to the shift value, theclock is then reset by 1 symbol,

[0197] slow locking: the initial value is equal to the sign of the shiftvalue: +1 or −1 or 0,the shift value defining the number of symbolsnecessary to perform resetting of the clock.

[0198] An indication of synchronization of the local symbol clock 82 istransmitted by the circuit 1 via the port rxa_sync. When rxa_sync=1, thelocal symbol clock is set, and the principal peak always appears at thesame position in the symbol window. When rxa_sync=0, the resetting ofthe local symbol clock 82 is active.

[0199] The local symbol clock block 82 (FIG. 7) receives a referenceclock signal rx_ckref. The rising edges of this clock should be spacedapart exactly by one symbol period. This signal is internally treated asa datum in the circuit, the rising edge is detected in order toinitialize a counter serving as basis for the internal control of thereference symbol clock reference_symbol_clock, for the acquisition stage40. This internal clock is used to calculate the clock shift instruction85 and possibly for synchronizing the information coming from theacquisition stage 40.

[0200] Two possibilities may be envisaged for calculating the symbolclock shift instruction:

[0201] either from the position of the principal peak in the symbolwindow (main_peak_position); in this case, whatever the locking mode ofthe local clock signal, the clock shift information is correct and isproduced immediately;

[0202] or from the local symbol clock (local_symbol_clock) 82, in thecase of the rapid locking mode of the local symbol clock; the clockshift information is correct, and a symbol appears after the appearanceof the new peak and, in the case of the slow mode, the clock shiftinformation is incorrect during the X local clock reset symbols.

[0203] The clock shift information produced is directly compatible withthe transmitter 2, the low weight bit defining {fraction (1/16)}th of apulse. The calculation of this information of shift made in theacquisition stage 40 or 48 is precise to ⅛th of a pulse: the low weightbit of the instruction is always null, evidently so when eight samplesare processed per pulse. The shift information is transmitted by thecircuit 1 in serial form via the port rxa_shift.

[0204] The determination of binary data is performed by means of thelocal symbol clock 82 (local_symbol_clock), which defines the instant ofcapture of the dot and cross information.

[0205] In DBPSK modulation, the correlation peaks appear uniquely on thedot signal; the sign of the peak corresponds to the binary information.In DQPSK modulation, the peaks are present alternately on the dot signaland the cross signal; the sign of the peak and the signal on which theyoccur permit the two bits of information to be decoded. The followingtable illustrates the decoding of data: max absolute symbol decodedvalue sign of peak (I, Q) phase jump dot + 00    0  cross − 10 −90° dot− 11 180° cross + 01 +90°

[0206] These two bits of information are transmitted from the circuit 1in serial form via the port rxa_data, the first corresponding to the bitI and the second to the bit Q.

[0207] The acquisition stage 40 incorporates a self-test mechanism basedon a 2⁹−1 random data generator identical to that of the transmitter 2.It permits verifying that the data generated by the transmitter 2 arecorrectly decoded in the acquisition stage 40; rxa_errber is then=0.

[0208] For this, the transmitter 2 should be in the TRAFFIC mode and useonly the acquisition code. The looping of the transmitter 2 to thereceiver 4 can be performed externally at the level of the circuit 1, orinternally.

[0209] Starting from the values of dot and cross, an automatic frequencycontrol command CAF is generated at the position of the peak of greatestamplitude defined by the local clock 82. This information characterizesthe frequency shift of the clock of the receiver 4 with respect to thatof the transmitter 2; the CAF bit, calculated at each symbol andtransmitted via the port rxa_caf, gives the direction of this shift.

[0210] A frequency shift induces the appearance of a parasitic peak onthe path not containing the correlation peak (cross in DBPSK, dot orcross in DQPSK).

[0211] In DBPSK, the module 48 of stage 40 calculates the CAF bit by thefunction XOR(sign(dot), sign(cross)) at the position of the principalpeak.

[0212] In DQPSK, if the correlation peak is present on the dot path, theCAF bit=XOR(sign(dot), sign(cross)); if not, (peak on cross), the CAFbit=NOT(XOR(sign(dot), sign(cross)).

[0213] The internal clock rxa_ckint is transmitted from the circuit 1via the port rxa_ck.

[0214] The reference symbol clock (reference_symbol_clock) istransmitted to the exterior in the form of a validation signalrxa_ensymb, of duration one internal clock period of the acquisitionstage (rxa_ckint). This validation signal permits marking the low weightbit of all the output information in series rxa_power, rxa_shift,rxa_nbacc, rxa_data.

[0215] The local symbol clock 82 (local_symbol_clock) is likewisetransmitted from the acquisition stage 40 to the traffic control stage42 (rxa_symb_clock), to permit utilization of this circuit in thecontext of an asynchronous link. In the case of an asynchronous link,the local symbol clock of the acquisition stage 40 directly pilots thetraffic control stage 42. The definition of the type of link,synchronous or asynchronous, is made by programming.

[0216] Internal signals (mf_i, mf_q, dot, cross, rimp, rimp_pond) may betransmitted via the port rxa_ts in order to be displayed on anoscilloscope.

[0217]FIG. 10 illustrates the internal architecture of the trafficcontrol stage 42.

[0218] The basic functions of this stage are:

[0219] the control of the clocks,

[0220] the correlation of baseband information by traffic sequences,

[0221] the post-treatment of correlation outputs,

[0222] differential multiplication,

[0223] the determination of the received binary data,

[0224] the estimation of power,

[0225] the evaluation of the clock shift command,

[0226] the output of clocks and data,

[0227] the display of internal signals.

[0228] The inputs and outputs relating to the traffic control stage 42are:

[0229] With the exterior:

[0230] rx_resetb: reset to zero for initialization;

[0231] rx_ckref: reference symbol clock,

[0232] rxt_ck: traffic path clock,

[0233] rxt_ensymb: validation of symbols,

[0234] rxt_endata: validation of data,

[0235] rxt_data: binary data,

[0236] rxt_powcmd: power control,

[0237] rxt_shiftm: symbol clock shift information (high weight)

[0238] rxt_shiftl: symbol clock shift information (low weight),

[0239] rxt_errber: data generator error indication

[0240] rxt_ts: output port for observability of symbols.

[0241] With the input stage 30:

[0242] rxt_ckint: base clock of traffic control stage 42,

[0243] rxt_i: input of traffic stage, path I,

[0244] rxt_q: input of traffic stage, path q.

[0245] With the acquisition stage 40:

[0246] rxa_symb_clock: local symbol clock for asynchronous link.

[0247] To make the traffic control stage 42 operational, it is necessaryto program traffic sequences (Rx traffic codes) and the code selectionmask (Rx code mask).

[0248] In operation, the traffic control stage 42 receives a referencesymbol clock rx_ckref. This clock is used in the acquisition controlstage 40 and traffic control stage 42 of the receiver 4.

[0249] The rising edges of this clock should be spaced apart by exactlyone symbol period.

[0250] This signal is treated as a datum internally of the circuit; therising edge is detected in order to initialize a counter serving as theinternal basis of the internal control of a second reference symbolclock 90 (reference_symbol_clock) incorporated in the second clockcontrol module 58.

[0251] This internal clock 90 is used to pilot the set of processes ofthe traffic control stage 42 and particularly the correlators 92.

[0252] If the circuit is used in the context of an asynchronous link,the traffic control stage 42 is directly piloted by the local symbolclock of the acquisition stage 40 rxa_symb_clock, that is,local_symbol_clock=rxa_symbol_clock.

[0253] In the embodiment illustrated by FIG. 10, a bank of thirty-twosliding correlators 92 performs the correlations between the basebandinformation after shaping rxt_i and rxt_q and the traffic sequencesprovided by a code table 94 and a masking module 96. The maximum lengthof the correlation sequences is 128 pulses.

[0254] The correlators 92 are piloted by means of the second localsymbol clock 90 (local_symbol_clock). They are set to the maximum valueof the correlation peak and are used for the determination of binarydata and the extraction of power.

[0255] The circuit processes two, four, or eight samples per pulse. Inthe whole stage of traffic control 42, a single sample per pulse istaken into account; this is why the I and Q information is serialized soas to reduce the material necessary for processing.

[0256] This serialization is performed by means of a signal i_qbar whichoscillates at a frequency two times lower than the sampling frequency.When i_qbar=1, the information is linked to the path I; if not, itcorresponds to the path Q.

[0257] Starting from the second local symbol clock 90, a validationsignal en_symb_middle is generated, of duration two periods of thesampling clock. This signal marks the first sample (one item ofinformation I and one item of information Q) of the symbol, and is usedfor:

[0258] initializing the accumulator at each start of symbol,

[0259] piloting the reading module 94 for code coefficients stored inRAM memory, and

[0260] controlling the serialization of the outputs of the thirty-twocorrelators 92.

[0261] Another en_chip_middle signal identifies the pulse sample whichis taken into account in the MIDDLE path.

[0262] The correlators are cascaded so as to produce a serial streamcor_m 100 from correlation values. This serial stream cor_m is appliedto the input of the second differential demodulation stage 52; thesixty-four serialized values, starting from the start of the symbol,have the form: 0I, then 0Q, then 1I, then 1Q, then 2I, then 2Q, endingat 31Q.

[0263] Two other banks of thirty-two sliding correlators, of the sametype as those of the path M, perform analogous processing, but areslightly phase shifted.

[0264] The phase shift between the paths E and L with respect to thepath M may take two values: ¼ pulse or ½ pulse (the path E is advancedand the path L is delayed).

[0265] From the local symbol clock 90, and as a function of programming,two validation signals, of duration two sampling clock periods, aregenerated: en_early and en_late. These signals mark the first symbolsamples which will be processed by the path E and the path L.

[0266] Two other signals, en_chip_early and en_chip_late, identify thepulse samples which are taken into account, respectively in the path Eand in the path L. Two serial streams, respectively cor_e 102 and cor_l104, are produced at the output of the two paths E and L and are appliedto the input of the second differential modulation stage 52.

[0267] The code allocation mask 96 permits selecting the codes which itis desired to use in the traffic control stage 42; the binary rate isdirectly connected to the number of validated codes in the mask 96.

[0268] A thirty-two bit register contains the mask mask_rx(31:0). If thebit mask_rx(i)=1, then the code i is valid; if not, the code i is notused.

[0269] The mask is used:

[0270] to generate the validation signal rxt_endata, which marks thecodes used,

[0271] to pilot the corresponding correlators.

[0272] When the mask is modified, the new instruction is immediatelytaken into account for the correlators. On the other hand, the nextrxt_ensymb is awaited to modify the validation signal rxt_endata.

[0273] In the traffic phase, the rate of a source may be adapted bymodifying the number of codes which are allocated to it.

[0274] Starting from path M correlation outputs (cor_m), differentialdemodulation is carried out, that is, the calculation of the dot andcross information, dot being the real portion of the result of thecomplex multiplication 112 of the correlation output with this sameoutput delayed by the duration of a symbol, and cross the imaginaryportion.

[0275] The following equations illustrate the calculation performed;I(n) and Q(n) correspond to the correlation outputs, and I(n−1) andQ(n−1) to the delayed outputs:

dot=I(n)I(n−1)+Q(n)Q(n−1)

cross=I(n−1)Q(n)−I(n)Q(n−1)

[0276] This dot and cross information, for each of the thirty-two codes,is calculated serially and defines the dotcross signal 114.

[0277] The determination of the binary data is performed from thedotcross signal 114.

[0278] In DBPSK modulation, the correlation peaks appear solely on thedot information, the sign of the peak corresponding to the binaryinformation. In DQPSK modulation, the peaks are present alternately onthe dot information and the cross information, the sign of the peak andthe path on which it is located enabling the two bits of information tobe decoded.

[0279] The choice of modulation type is made by programming. The datadecoding table is illustrated by the following table: Max absoluteDecoded symbol Phase jump value Sign of the peak (I, Q) lump dot + 00 0°cross − 10 −90° dot − 11 180° cross + 01 90°

[0280] The processing of the thirty-two codes is performed serially. Thesixty-four bits of calculated information are transmitted to the circuit1 in serial form via the port rxt_data, the first pair corresponding tothe information bits relating to code 0,the first being the bit I andthe second the bit Q, the second pair to code 1, etc.

[0281] The traffic control stage 42 incorporates a self-test mechanismbased on a 2⁹−1 random data generator identical to that of thetransmitter 2. It permits verifying that the data generated by thetransmitter 2 are correctly decoded in the traffic control stage 42;rxt_errber is then=0.

[0282] For this, the transmitter 2 has to be in traffic mode andsynchronized with respect to the reference symbol clock, and the trafficcontrol stage 42 has to have the same code mask. The looping of thetransmitter 2 to the receiver 4 can be effected externally at the levelof the circuit or internally.

[0283] The signal energy I2+Q2 is calculated from the correlationoutputs 92 for the three paths M, E and L (cor_m, cor_e, cor_l).

[0284] This information, for each of the thirty-two codes, is calculatedserially and defines the signal pow_m for the path M, pow_e for the pathE, and pow_l for the path L. The information is stable for two samplingperiods.

[0285] A low-pass filter on the path M permits improving the estimationof power by reducing noise.

[0286] Programming permits choosing as the signal used for powerestimation one of the following signals:

[0287] pow_m: energy on the path M,

[0288] abs(dot): result of differential demodulation in DBPSK,

[0289] MAX (abs(dot), abs(cross)): result of the differentialdemodulation in DQPSK.

[0290] The dot and cross items of information appear serially on thedotcross signal.

[0291]FIG. 11 shows the internal structure of the architecture of theselection block A1 and the filtering block A2 for the path M powersignal. The filtering block A1 is a recursive type filter, and of depthprogrammable up to n=512 symbols. At the filter output, the signalrimp_m contains the thirty-two items of information relating to thethirty-two codes, each item of information being stable for two samplingperiods.

[0292]FIG. 12 shows the internal structure of the filtering block B forthe path E and L power signals. This filter takes into account thedifference between the energies of paths E and L and permits calculatingan estimation of the separation of power between these two paths. Thisinformation is useful for the calculation of the clock shift.

[0293] The filtering block B is a low-pass filter identical to thefilter present in the path M. The data processed by this filter arelikewise signed, but the sign bit is not necessarily null. These datamay be positive or negative.

[0294] The depth of the filter is identical to the depth of the path Mfilter. At the filter output, the signal rimp_el contains the thirty-twoitems of information relating to the thirty-two codes, each item ofinformation being stable for two sampling periods. These items ofinformation are signed.

[0295] The information rimp_m, coming from the low-pass filter A2 on thepath M, corresponds to an estimate of the power for the thirty-twocodes.

[0296] From this, a power command (powcmd) coded on two bits iscalculated.

[0297]FIG. 13 illustrates the coding of the power command.

[0298] The program word {SR: rxt_pow_ref} fixes the power reference, andthe word {SR: rxt_pow—delta} defines a range around this reference.

[0299] The powcmd command is transmitted from the circuit for eachsymbol and for each code in serial form via the port rxt_powcmd (LSBthen MSB).

[0300] Starting from the estimate of power (rimp_m) on the path M, andfrom the estimate of the separation of power (rimp_el) between the pathsE and L, a symbol clock shift instruction is calculated.

[0301] This clock shift information: shift (3:0) constitutes a signed4-bit word (value comprised in the interval [−7:+7], the low weight bitdefining {fraction (1/16)}th of a pulse.

[0302] In contrast to the acquisition stage 40, where the calculationperformed gives an instruction accurate to ⅛th of a pulse (the lowweight bit is always null), in the traffic control stage 42, theinstruction is accurate to {fraction (1/16)}th of a pulse.

[0303] The principle of the calculation of the symbol clock shiftinstruction rests on the conversion of a power separation into a timeseparation. The function connecting these two quantities is quasi-lineararound zero and may be written:${Shift} = {\frac{Gr}{Gc}*\frac{rimp\_ el}{rimp\_ m}}$

[0304] Gr corresponds to the gain of resolution which permits the LSB ofthe command to be defined. The resolution of the tracking command isfixed at {fraction (1/16)}th of a pulse; consequently the value of Gr is16.

[0305] Gc corresponds to the conversion gain, which is the slope of theconversion of time into power separation and depends on the shape of thecorrelation peak, and consequently of the pulse filter, and on the shiftof the paths E and L.

[0306] The following table gives the approximate values of the parameterGc, as well as the coding of the corresponding program word {SR:rxt_div_coef}. Pulse filter E-L-Δ Gc {SR: rxt_dic_coef}. RECT ¼ chip 3 0RECT ½ chip 2 1 damping rate 0.4 ¼ chip 3 0 damping rate 0.4 ½ chip 3 0

[0307] The shift information is transmitted from the circuit (shift), ateach symbol and for each code, in a serial and parallel form, via theport rxt_shift1 for the two low weight bits (rxt_shift(0), thenrxt_shift(1)) and the port rxt_shiftm for the two high weight bits(rxt_shift(2), then rxt_shift (3)).

[0308] The internal clock rxt_ckint is transmitted from the circuit viathe port rxt_ck.

[0309] The local symbol clock is transmitted to the exterior in the formof a validation signal rxt_ensymb, of duration two periods of theinternal clock (rxt_ckint) of the traffic control stage 42. Thisvalidation signal rxt_ensymb permits marking the information bitsrelating to the code 0: rxt_data, rxt_shift1, rxt_shiftm, rxt_powcmd.

[0310] The signal rxt_endata permits marking the information relating tothe codes validated by the mask mask_rx.

[0311] Internal signals (dotcross, cor_m, cor_e, cor_l, pow_m, pow_e,pow_l, powj, rimp_m, rimp_el) may be transmitted via the port rxt_ts soas to display them on an oscilloscope.

[0312] The circuit according to the invention is programmable via asimple interface comprising an address bus and a data bus and twocontrol signals. The program words are grouped by bank. An address pg_adon three bits permits selecting a bank; the words are entered in octetsvia a specific bus pg. The table below gives a brief description of thedifferent programming banks. @ pg_ad(2:O) Description 0 “000” SerialRegister 1 “001” Rx code mask 2 “010” Tx code mask 3 “011” RxAcquisition code 4 “100” Rx Traffic codes 5 “101” Tx codes 6 “110” Txclock shift 7 “111” reset

[0313] The entries relating to the programming aspect are:

[0314] pg(7:0): input of program octets,

[0315] pg_ck: clock for taking into account information on pg toward theshift register; the rising edge is the active edge of the signal,

[0316] pg_ld: command to take new programming into account (not used forsequences),

[0317] pgad(2:0): selection of program bank.

1. Digital transmission/reception circuit (1) intended to be mounted onat least one source and on at least one concentrator exchanging binarysymbols with the said source, the said circuit (1) comprising atransmitter (2) capable of transmitting the said binary symbols and areceiver (4) capable of receiving symbols transmitted by a source, thecircuit (1) being characterized in that the transmitter (2) comprises afirst module (20) intended to generate at least one binary code foreffecting the spectral spreading of symbols to be transmitted and asecond module (22) intended to generate at least one internal clocksignal for synchronizing the reception of symbols transmitted by asource, and in that the said receiver comprises means (46, 48) fordetecting new sources of transmission and means (49) for generatingsynchronization signals and power control signals corresponding to eachnew source detected.
 2. Circuit according to claim 1, characterized inthat the said receiver comprises an input stage (30), an acquisitioncontrol stage (40), and a traffic control stage (42), the input stage(30) comprising a block (32) for shaping received signals, a pulsefilter (34) intended to limit the spectrum of the received signals, astage (36) for sampling the filtered signals and transmitting thefiltered data, on the one hand, to the acquisition control stage (40)which extracts from the said filtered data the power and time shiftinformation of the received symbols with respect to a base clock of thereceiver (4), and on the other hand, to the traffic control stage (42)which extracts from the filtered data the transmitted binary informationand the power and time shift data of the received symbols with respectto the base clock of the receiver (4).
 3. Circuit according to claim 2,characterized in that the acquisition control stage (40) comprises afirst differential demodulation module (44), a module (46) forgenerating an acquisition signal representing synchronization signalsand power control signals corresponding to each new transmission source,a module (48) for processing the generated acquisition signal, and afirst clock control block (49).
 4. Circuit according to claim 2,characterized in that the traffic control stage (42) comprises a module(50) for correlation of previously processed data with the codesassociated with these data, a module (52) for differential demodulationof the correlated data, a calculation module (54) intended fordetermining the synchronization signals and the power control signalscorresponding to each detected transmission source.